The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2013
Filed:
Mar. 27, 2009
Jonathan Owen, Northborough, MA (US);
Guhan Krishnan, Chelmsford, MA (US);
Carl D. Dietz, Round Rock, TX (US);
Douglas Richard Beard, Austin, TX (US);
William K. Lewchuk, Pflugerville, TX (US);
Alexander Branover, Chestnut Hill, MA (US);
Jonathan Owen, Northborough, MA (US);
Guhan Krishnan, Chelmsford, MA (US);
Carl D. Dietz, Round Rock, TX (US);
Douglas Richard Beard, Austin, TX (US);
William K. Lewchuk, Pflugerville, TX (US);
Alexander Branover, Chestnut Hill, MA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.