The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2013
Filed:
May. 08, 2010
Eike Linn, Wuerselen, DE;
Carsten Kuegeler, Hamm, DE;
Roland Daniel Rosezin, Bernau, DE;
Rainer Waser, Aachen, DE;
Eike Linn, Wuerselen, DE;
Carsten Kuegeler, Hamm, DE;
Roland Daniel Rosezin, Bernau, DE;
Rainer Waser, Aachen, DE;
Forschungszentrum Juelich GmbH, Juelich, DE;
Rheinish-Westfaelische Technische Hochschule Aachen (RWTH), Aachen, DE;
Abstract
Disclosed is a memory element, a stack, and a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V, it can be transferred into the likewise high-impedance state 1. By applying a read voltage V, the magnitude of which is smaller than the write voltages Vand V, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been disclosed, using an array comprising the memory elements which can be turned into a gate for arbitrary logic operations.