The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2013

Filed:

Jun. 25, 2010
Applicants:

Azeez Jennudin Bhavnagarwala, Danbury, CT (US);

Stephen V. Kosonocky, Wilton, CT (US);

Carl John Radens, LaGrangeville, NY (US);

Kevin Geoffrey Stawiasz, Bethel, CT (US);

Inventors:

Azeez Jennudin Bhavnagarwala, Danbury, CT (US);

Stephen V. Kosonocky, Wilton, CT (US);

Carl John Radens, LaGrangeville, NY (US);

Kevin Geoffrey Stawiasz, Bethel, CT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3187 (2006.01);
U.S. Cl.
CPC ...
Abstract

A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of <1 ms/DC sweep at <2 mV or <1 nA resolution accuracy of variations in voltage or current of the device under test. Salient features of proposed circuit architecture include a programmable ramp voltage generator that stimulates the device under test, a dual input 9-11 bit cyclic ADC that captures input and output DC voltage/current signals to/from the device under test, a 2 Kb latch bank that captures 9-11 bit streams for each measurement point in a DC sweep of programmable granularity and a clocking and control scheme that enables continuous measurement and stream out of digital data blocks from which the analog characteristics of the devices under test are reconstructed post measurement.


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