The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2013

Filed:

Aug. 01, 2011
Applicants:

Se-young Jeong, Suwon-si, KR;

Ho-jin Lee, Seoul, KR;

Ho-geon Song, Suwon-si, KR;

Jae-hyun Phee, Incheon, KR;

Inventors:

Se-young Jeong, Suwon-si, KR;

Ho-jin Lee, Seoul, KR;

Ho-geon Song, Suwon-si, KR;

Jae-hyun Phee, Incheon, KR;

Assignee:

Samsung Electronics Co., Ltd., Samsung-ro, Yeongton-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/00 (2006.01); H01L 23/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.


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