The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2013

Filed:

Jan. 13, 2012
Applicants:

Yu-lin Yen, Taipei, TW;

Shih-ming Chen, Hsinchu, TW;

Hsi-chien Lin, Zhubei, TW;

Yu-lung Huang, Daxi Township, TW;

Tsang-yu Liu, Zhubei, TW;

Inventors:

Yu-Lin Yen, Taipei, TW;

Shih-Ming Chen, Hsinchu, TW;

Hsi-Chien Lin, Zhubei, TW;

Yu-Lung Huang, Daxi Township, TW;

Tsang-Yu Liu, Zhubei, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01); H01L 23/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof.


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