The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2013
Filed:
Dec. 13, 2011
Mahbub Rashed, Santa Clara, CA (US);
Steven Soss, Cornwall, NY (US);
Jongwook Kye, Pleasanton, CA (US);
Irene Y. Lin, Los Altos Hills, CA (US);
James Benjamin Gullette, Wadesboro, NC (US);
Chinh Nguyen, Austin, TX (US);
Jeff Kim, San Jose, CA (US);
Marc Tarabbia, Pleasant Valley, NY (US);
Yuansheng MA, Santa Clara, CA (US);
Yunfei Deng, Sunnyvale, CA (US);
Rod Augur, Hopewell Junction, NY (US);
Seung-hyun Rhee, Fishkill, NY (US);
Scott Johnson, Wappingers Falls, NY (US);
Subramani Kengeri, San Jose, CA (US);
Suresh Venkatesan, Danbury, CT (US);
Mahbub Rashed, Santa Clara, CA (US);
Steven Soss, Cornwall, NY (US);
Jongwook Kye, Pleasanton, CA (US);
Irene Y. Lin, Los Altos Hills, CA (US);
James Benjamin Gullette, Wadesboro, NC (US);
Chinh Nguyen, Austin, TX (US);
Jeff Kim, San Jose, CA (US);
Marc Tarabbia, Pleasant Valley, NY (US);
Yuansheng Ma, Santa Clara, CA (US);
Yunfei Deng, Sunnyvale, CA (US);
Rod Augur, Hopewell Junction, NY (US);
Seung-Hyun Rhee, Fishkill, NY (US);
Scott Johnson, Wappingers Falls, NY (US);
Subramani Kengeri, San Jose, CA (US);
Suresh Venkatesan, Danbury, CT (US);
GLOBALFOUNDRIES, Inc., Grand Cayman, KY;
Abstract
A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.