The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2013
Filed:
Jul. 18, 2012
Harry S. Barowski, Boeblingen, DE;
Maarten J. Boersma, Holzerlingen, DE;
Silvia M. Mueller, Altdorf, DE;
Tim Niggemeier, Laatzen, DE;
Jochen Preiss, Boeblingen, DE;
Harry S. Barowski, Boeblingen, DE;
Maarten J. Boersma, Holzerlingen, DE;
Silvia M. Mueller, Altdorf, DE;
Tim Niggemeier, Laatzen, DE;
Jochen Preiss, Boeblingen, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is 'unordered', a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.