The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2013

Filed:

Feb. 08, 2012
Applicants:

Yutaka Shinagawa, Tokyo, JP;

Takeshi Kataoka, Tokyo, JP;

Eiichi Ishikawa, Tokyo, JP;

Toshihiro Tanaka, Tokyo, JP;

Kazumasa Yanagisawa, Tokyo, JP;

Kazufumi Suzukawa, Tokyo, JP;

Inventors:

Yutaka Shinagawa, Tokyo, JP;

Takeshi Kataoka, Tokyo, JP;

Eiichi Ishikawa, Tokyo, JP;

Toshihiro Tanaka, Tokyo, JP;

Kazumasa Yanagisawa, Tokyo, JP;

Kazufumi Suzukawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has a maximum variation width of a threshold voltage for memorizing an information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.


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