The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2013

Filed:

Dec. 09, 2010
Applicants:

Hajin Lim, Seoul, KR;

Myungsun Kim, Hwaseong-si, KR;

Hoi Sung Chung, Hwaseong-si, KR;

Jinho DO, Hwaseong-si, KR;

Weonhong Kim, Suwon-si, KR;

Moonkyun Song, Anyang-si, KR;

Dae-kwon Joo, Osan-si, KR;

Inventors:

Hajin Lim, Seoul, KR;

Myungsun Kim, Hwaseong-si, KR;

Hoi Sung Chung, Hwaseong-si, KR;

Jinho Do, Hwaseong-si, KR;

Weonhong Kim, Suwon-si, KR;

Moonkyun Song, Anyang-si, KR;

Dae-Kwon Joo, Osan-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.


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