The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2013

Filed:

May. 26, 2011
Applicants:

William F. Clark, Jr., Essex Junction, VT (US);

Stephen E. Luce, Underhill, VT (US);

Inventors:

William F. Clark, Jr., Essex Junction, VT (US);

Stephen E. Luce, Underhill, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.


Find Patent Forward Citations

Clark, Jr., William. (2013). Charge breakdown avoidance for mim elements in soi base technology and method (U.S. Patent No. 8575668). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8575668

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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