The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8575495 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 05, 2013

Filed:

Sep. 22, 2011
Applicants:

Shigetsugu Muramatsu, Nagano, JP;

Satoshi Sunohara, Nagano, JP;

Inventors:

Shigetsugu Muramatsu, Nagano, JP;

Satoshi Sunohara, Nagano, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/16 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0269 (2013.01);
Abstract

A wiring substrate includes a wiring pattern, which includes an upper surface forming a desired recognition mark, and a solder resist layer, which covers the wiring pattern. The solder resist layer includes a recess that entirely exposes the upper surface of the wiring pattern. The solder resist layer includes a solder resist layer formed at a region corresponding to the recess and a solder resist layer formed outside the recess. The recess entirely exposes the upper surface of the wiring pattern as the recognition mark, and the solder resist layer is formed at portions outside the upper surface of the wiring pattern.


Find Patent Forward Citations

Muramatsu, Shigetsugu. (2013). Wiring substrate, semiconductor device, and method for manufacturing wiring substrate (U.S. Patent No. 8575495). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8575495

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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