The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8570068 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 29, 2013

Filed:

Apr. 28, 2010
Applicants:

Chan-hong Chern, Palo Alto, CA (US);

Fu-lung Hsueh, Cranbury, NJ (US);

Ming-chieh Huang, San Jose, CA (US);

Bryan Sheffield, Austin, TX (US);

Chih-chang Lin, San Jose, CA (US);

Inventors:

Chan-Hong Chern, Palo Alto, CA (US);

Fu-Lung Hsueh, Cranbury, NJ (US);

Ming-Chieh Huang, San Jose, CA (US);

Bryan Sheffield, Austin, TX (US);

Chih-Chang Lin, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.


Find Patent Forward Citations

Chern, Chan-Hong. (2013). Circuit for reducing negative bias temperature instability (U.S. Patent No. 8570068). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8570068

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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