The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2013

Filed:

May. 27, 2011
Applicants:

Atsuo Isobe, Isehara, JP;

Yoshinori Ieda, Atsugi, JP;

Keitaro Imai, Yokohama, JP;

Kiyoshi Kato, Atsugi, JP;

Yuto Yakubo, Isehara, JP;

Yuki Hata, Atsugi, JP;

Inventors:

Atsuo Isobe, Isehara, JP;

Yoshinori Ieda, Atsugi, JP;

Keitaro Imai, Yokohama, JP;

Kiyoshi Kato, Atsugi, JP;

Yuto Yakubo, Isehara, JP;

Yuki Hata, Atsugi, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.


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