The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2013

Filed:

Dec. 22, 2009
Applicants:

Vladimir Aleksandar Zivkovic, 'S-Hertogenbosch, NL;

Frank Van Der Heijden, Eindhoven, NL;

Geert Seuren, Roggel, NL;

Steven Oostdijk, Albasserdam, NL;

Mario Konijnenburg, Best, NL;

Inventors:

Vladimir Aleksandar Zivkovic, 'S-Hertogenbosch, NL;

Frank van der Heijden, Eindhoven, NL;

Geert Seuren, Roggel, NL;

Steven Oostdijk, Albasserdam, NL;

Mario Konijnenburg, Best, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A test interface circuit operates with different types of core circuits. As consistent with various embodiments, the test interface circuit includes a test input register (TIR) configured to select an operating mode and a plurality of test point registers (TPRs). Each TPR is configured to control signals passed from the input port to a mixed-signal core circuit, responsive to the received test input signals and the operating mode selected by a TIR. In a static mode, each TPR provides serial access to digital inputs and outputs of a mixed-signal core circuit. In a bypass mode, each TPR bypasses TPR slices to preserve test time in response to the TPR being chained to other ones of the TPRs during integration of at least two mixed-signal cores.


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