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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8563404 B1

PDFFull Text
Date of Patent:
Oct. 22, 2013

Filed:

Jul. 28, 2011

Process for dividing wafer into individual chips and semiconductor chips

Applicant:

Toshiyuki Kosaka, Yokohama, JP;

Inventor:

Toshiyuki Kosaka, Yokohama, JP;

Assignee:

Sumitomo Electric Device Innovations, Inc., Kanagawa, JP;

Attorney:

Smith, Gambrell & Russell, LLP

Primary Examiner:

Ha Tran T Nguyen

Assistant Examiner:

Thai T Vuong

Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/30 (2006.01); H01L 21/46 (2006.01); H01L 21/00 (2006.01); H01L 29/15 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
Abstract

A process to divide a wafer into individual chips is disclosed. The process (1) etches semiconductor layers for an active device to form two grooves putting the virtual cut line therebetween, where the semiconductor wafer is to be divided along the virtual cut line; (2) etches the substrate in a region including the virtual cut line but offset from the groove from the back surface thereof so as to expose the semiconductor layers in the primary surface; and (3) etches the semiconductor layer exposed in step (2).

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Kosaka, Toshiyuki. (2013). Process for dividing wafer into individual chips and semiconductor chips (U.S. Patent No. 8563404). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8563404

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