The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2013

Filed:

Dec. 02, 2011
Applicants:

Dean C. Regan, Moorpark, CA (US);

Keisuke Shinohara, Thousand Oaks, CA (US);

Andrea Corrion, Oak Park, CA (US);

Ivan Milosavljevic, Thousand Oaks, CA (US);

Miroslav Micovic, Thousand Oaks, CA (US);

Peter J. Willadsen, Acton, CA (US);

Colleen M. Butler, Camarillo, CA (US);

Hector L. Bracamontes, Lawndale, CA (US);

Bruce T. Holden, Torrance, CA (US);

David T. Chang, Calabasas, CA (US);

Inventors:

Dean C. Regan, Moorpark, CA (US);

Keisuke Shinohara, Thousand Oaks, CA (US);

Andrea Corrion, Oak Park, CA (US);

Ivan Milosavljevic, Thousand Oaks, CA (US);

Miroslav Micovic, Thousand Oaks, CA (US);

Peter J. Willadsen, Acton, CA (US);

Colleen M. Butler, Camarillo, CA (US);

Hector L. Bracamontes, Lawndale, CA (US);

Bruce T. Holden, Torrance, CA (US);

David T. Chang, Calabasas, CA (US);

Assignee:

HRL Laboratories, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate including silicon, forming first sidewalls of a first material on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a material layer over the mesa, planarizing the material layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the material layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.


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