The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2013
Filed:
Jun. 16, 2009
Donald O'riordan, Sunnyvale, CA (US);
Prabal K. Bhattacharya, Cupertino, CA (US);
Walter Hartong, Isen, DE;
Richard John O'donovan, San Jose, CA (US);
Donald O'Riordan, Sunnyvale, CA (US);
Prabal K. Bhattacharya, Cupertino, CA (US);
Walter Hartong, Isen, DE;
Richard John O'Donovan, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Systems and methods for simulating and verifying a design are contemplated. Various embodiments determine a set of verification rules for a design, wherein the verification rules use a PSL or SVA syntax in a SPICE netlist to describ a property of the circuit design. The state of a circuit at a simulated first time, t, can be determined. The state at the first time, t, may be analyzed to determine if a triggering event has occurred. Based on the occurrence of the triggering event, the systems and methods can verify the state at the first time, t, against the set of verification rules. Some embodiments of the systems and methods described herein can include a mixed-signal circuit including an analog portion and a digital portion, and the analog portion, the mixed-signal portion, or both, may be simulated and verified.