The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2013
Filed:
Aug. 20, 2009
Shunsaku Muraoka, Osaka, JP;
Yoshihiko Kanzawa, Osaka, JP;
Satoru Mitani, Osaka, JP;
Koji Katayama, Nara, JP;
Kazuhiko Shimakawa, Osaka, JP;
Satoru Fujii, Osaka, JP;
Takeshi Takagi, Kyoto, JP;
Shunsaku Muraoka, Osaka, JP;
Yoshihiko Kanzawa, Osaka, JP;
Satoru Mitani, Osaka, JP;
Koji Katayama, Nara, JP;
Kazuhiko Shimakawa, Osaka, JP;
Satoru Fujii, Osaka, JP;
Takeshi Takagi, Kyoto, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (), (ii) a variable resistance element () having: lower and upper electrodes (,); and a variable resistance layer () whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (,), and (iii) a MOS transistor () formed on the substrate (), wherein the variable resistance layer () includes: oxygen-deficient transition metal oxide layers (-,-) having compositions MOand MO(where x<y) and in contact with the electrodes (,) respectively, and a diffusion layer region () is connected with the lower electrode () to form a memory cell (), the region () serving as a drain of the transistor () upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer ().