The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2013
Filed:
Mar. 23, 2012
Kuoyuan Hsu, San Jose, CA (US);
Ming-chieh Huang, San Jose, CA (US);
Young Suk Kim, Fremont, CA (US);
Subramani Kengeri, San Jose, CA (US);
Kuoyuan Hsu, San Jose, CA (US);
Ming-Chieh Huang, San Jose, CA (US);
Young Suk Kim, Fremont, CA (US);
Subramani Kengeri, San Jose, CA (US);
Abstract
An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit coupled with the memory bank. The interleaved memory circuit further includes a global control circuit coupled with the local control circuit, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell, where the second cycle is capable of enabling the local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.