The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2013
Filed:
May. 24, 2011
Brian E. Bakke, Rochester, MN (US);
Brian L. Bowles, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Robert E. Galbraith, Ii, Rochester, MN (US);
Adrian C. Gerhard, Rochester, MN (US);
Murali N. Iyer, Rochester, MN (US);
Daniel F. Moertl, Rochester, MN (US);
Mark J. Moran, Minneapolis, MN (US);
Gowrisankar Radhakrishnan, Rochester, MN (US);
Rick A. Weckwerth, Oronoco, MN (US);
Donald J. Ziebarth, Rochester, MN (US);
Brian E. Bakke, Rochester, MN (US);
Brian L. Bowles, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Robert E. Galbraith, II, Rochester, MN (US);
Adrian C. Gerhard, Rochester, MN (US);
Murali N. Iyer, Rochester, MN (US);
Daniel F. Moertl, Rochester, MN (US);
Mark J. Moran, Minneapolis, MN (US);
Gowrisankar Radhakrishnan, Rochester, MN (US);
Rick A. Weckwerth, Oronoco, MN (US);
Donald J. Ziebarth, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.