The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2013
Filed:
Nov. 09, 2010
Chen-yong Cher, Port Chester, NY (US);
Eren Kursun, Ossining, NY (US);
Gary W. Maier, Poughquag, NY (US);
Raphael Peter Robertazzi, Ossining, NY (US);
Chen-Yong Cher, Port Chester, NY (US);
Eren Kursun, Ossining, NY (US);
Gary W. Maier, Poughquag, NY (US);
Raphael Peter Robertazzi, Ossining, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Testing of a three-dimensional (3D) integrated circuit includes defining a first group of parts by a region and/or layer on the 3D integrated circuit. The testing further includes applying a first intensity of stress test conditions to the first group of parts. The testing also includes defining a second group of parts by a region and/or layer on the 3D integrated circuit that is different from the first group of parts. The testing further includes and applying a second intensity of stress test conditions to the second group of parts. The second intensity of stress test conditions is greater than the first intensity and is determined by sensitivities identified for each of the first and second group of parts. A determination is made whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.