The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2013
Filed:
Sep. 15, 2011
Yung-fa Lin, Hsinchu, TW;
Shou-yi Hsu, Hsinchu County, TW;
Meng-wei Wu, Hsinchu, TW;
Main-gwo Chen, Hsinchu County, TW;
Yi-chun Shih, Nantou County, TW;
Yung-Fa Lin, Hsinchu, TW;
Shou-Yi Hsu, Hsinchu County, TW;
Meng-Wei Wu, Hsinchu, TW;
Main-Gwo Chen, Hsinchu County, TW;
Yi-Chun Shih, Nantou County, TW;
Anpec Electronics Corporation, Hsinchu Science Park, Hsin-Chu, TW;
Abstract
A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.