The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2013

Filed:

Apr. 17, 2009
Applicants:

Issei Satoh, Itami, JP;

Michimasa Miyanaga, Osaka, JP;

Shinsuke Fujiwara, Itami, JP;

Hideaki Nakahata, Itami, JP;

Inventors:

Issei Satoh, Itami, JP;

Michimasa Miyanaga, Osaka, JP;

Shinsuke Fujiwara, Itami, JP;

Hideaki Nakahata, Itami, JP;

Assignee:

Sumitomo Electric Industries, Ltd., Osaka-shi, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C30B 23/00 (2006.01); C30B 25/00 (2006.01); C30B 28/12 (2006.01); C30B 28/14 (2006.01);
U.S. Cl.
CPC ...
C30B 23/00 (2013.01); C30B 25/00 (2013.01); C30B 28/12 (2013.01); C30B 28/14 (2013.01);
Abstract

There are provided a method for manufacturing a SiCAlNsubstrate having a reduced number of cracks and high processability, a method for manufacturing an epitaxial wafer, a SiCAlNsubstrate, and an epitaxial wafer. A method for manufacturing a SiCAlNsubstrateincludes the following steps. First, a Si substrateis prepared. A SiCAlNlayer (0<v<1, 0<w<1, 0<x<1, and 0<v+w+x<1) is then grown on the Si substrate at a temperature below 550° C.


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