The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2013
Filed:
Jul. 08, 2011
Shawn Murray, Portland, OR (US);
John Schadt, Bethlehem, PA (US);
Steven J. Fong, Santa Clara, CA (US);
Luan Phoc Chau, Portland, OR (US);
Thomas R. Gustafson, Banks, OR (US);
Shawn Murray, Portland, OR (US);
John Schadt, Bethlehem, PA (US);
Steven J. Fong, Santa Clara, CA (US);
Luan Phoc Chau, Portland, OR (US);
Thomas R. Gustafson, Banks, OR (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Two (or more) different, but complementary, families of integrated circuits having the same layout are developed simultaneously where the different families are achieved by changing one or more design parameters of transistors used to implement the integrated circuits. For example, a low-power (but low-speed) family of one or more ICs (e.g., for handheld applications) can be achieved by designing at least some transistors with relatively high threshold-voltage (Vt) levels, while a different, but complementary, high-speed (but high-power) family of one or more ICs (e.g., for server applications) can be achieved by designing corresponding transistors with relatively low Vt levels. In this way, the two families can share in common all but a very few masks used to fabricate the ICs of the different families.