The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2013

Filed:

Mar. 02, 2012
Applicants:

Pervez Aziz, Dallas, TX (US);

Hiroshi Kimura, San Jose, CA (US);

Amaresh Malipatil, San Jose, CA (US);

Inventors:

Pervez Aziz, Dallas, TX (US);

Hiroshi Kimura, San Jose, CA (US);

Amaresh Malipatil, San Jose, CA (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.


Find Patent Forward Citations

Aziz, Pervez. (2013). Low-power down-sampled floating tap decision feedback equalization (U.S. Patent No. 8537885). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8537885

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