The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Jul. 18, 2012
Soon Yoeng Tan, Wappingers Falls, NY (US);
Angeline Ho, Johor, MY;
Hendry Renaldo, Singapore, SG;
Andreas Knorr, Wappingers Falls, NY (US);
Scott Johnson, Wappingers Falls, NY (US);
Soon Yoeng Tan, Wappingers Falls, NY (US);
Angeline Ho, Johor, MY;
Hendry Renaldo, Singapore, SG;
Andreas Knorr, Wappingers Falls, NY (US);
Scott Johnson, Wappingers Falls, NY (US);
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Abstract
An approach for providing conversion of a planar design to a FinFET design is disclosed. Embodiments include: receiving a planar design having a plurality of diffusion regions; overlapping a plurality of parallel fin mandrels with a plurality of evenly-spaced parallel lines of a grid; snapping the diffusion regions to the grid based on the parallel lines; and generating a FinFET design based on the overlapping and the snapping. Embodiments include the parallel lines and the parallel fin mandrels being perpendicular to a poly orientation associated with the planar design, and determining a spacing length between the parallel lines; determining a plurality of edges of the diffusion regions that are parallel to the poly orientation; and cropping the diffusion regions until each of the edges has a length that is a multiple of the spacing length.