The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Sep. 15, 2011
Mei-hsuan Lin, Tainan, TW;
Chih-chan LU, Kaohsiung, TW;
Chih-hsun Lin, Tainan, TW;
Chih-kang Chao, Tainan, TW;
Ling-sung Wang, Tainan, TW;
Jen-pan Wang, Tainan, TW;
Mei-Hsuan Lin, Tainan, TW;
Chih-Chan Lu, Kaohsiung, TW;
Chih-Hsun Lin, Tainan, TW;
Chih-Kang Chao, Tainan, TW;
Ling-Sung Wang, Tainan, TW;
Jen-Pan Wang, Tainan, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.