The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Sep. 14, 2010
Amir Amirkhany, Sunnyvale, CA (US);
Chaofeng Huang, San Jose, CA (US);
Kambiz Kaviani, San Francisco, CA (US);
Wayne D. Dettloff, Cary, NC (US);
Kun-yung Chang, Los Altos, CA (US);
Amir Amirkhany, Sunnyvale, CA (US);
Chaofeng Huang, San Jose, CA (US);
Kambiz Kaviani, San Francisco, CA (US);
Wayne D. Dettloff, Cary, NC (US);
Kun-Yung Chang, Los Altos, CA (US);
Rambus Inc., Sunnyvale, CA (US);
Abstract
High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such 'differential' or 'non-uniform' sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.