The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2013

Filed:

May. 23, 2011
Applicants:

Albert Ratnakumar, San Jose, CA (US);

Qi Xiang, San Jose, CA (US);

Jun Liu, Milpitas, CA (US);

Inventors:

Albert Ratnakumar, San Jose, CA (US);

Qi Xiang, San Jose, CA (US);

Jun Liu, Milpitas, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuits may be provided that include memory elements that produce output control signals and corresponding programmable logic circuitry that receives the output control signals from the memory elements. The memory elements may include bistable storage elements formed from circuits such as cross-coupled inverters. The inverters may include n-channel metal-oxide-semiconductor transistors with p-metal gate conductors and n-channel metal-oxide-semiconductor transistors with p-metal gate conductors. These gate conductor assignments are the reverse of the gate conductor assignments used in the n-channel and p-channel transistors in other circuitry such as the programmable logic circuitry. The reversed gate conductor assignments increase the threshold voltages of the transistors in the memory elements to improve reliability in scenarios in which the memory elements are overdriving pass transistors in the programmable logic circuitry.


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