The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2013

Filed:

Sep. 23, 2011
Applicants:

Jin-bum Kim, Seoul, KR;

Chul-sung Kim, Seongnam-si, KR;

Yu-gyun Shin, Seongnam-si, KR;

Dae-yong Kim, Yongin-si, KR;

Joon-gon Lee, Seoul, KR;

Kwang-young Lee, Suwon-si, KR;

Inventors:

Jin-Bum Kim, Seoul, KR;

Chul-Sung Kim, Seongnam-si, KR;

Yu-Gyun Shin, Seongnam-si, KR;

Dae-Yong Kim, Yongin-si, KR;

Joon-Gon Lee, Seoul, KR;

Kwang-Young Lee, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8249 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.


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