The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2013

Filed:

Dec. 23, 2009
Applicants:

Prakash Gopalakrishnan, Pittsburgh, PA (US);

Alisa Yurovsky, Pittsburgh, PA (US);

Inventors:

Prakash Gopalakrishnan, Pittsburgh, PA (US);

Alisa Yurovsky, Pittsburgh, PA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A computer-readable medium stores a specification for a circuit layout. The specification includes: a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or more device constraints for devices in a same room. The configuration of rooms may include a tree-structure for the rooms. The room constraints may include a common symmetry line for a first room and a second room. The device constraints may include a self-symmetry constraint for a first device about a symmetry line in a first room. The device constraints may include a symmetry constraint for a first device and a second device about a symmetry line in a first room. The devices may include analog or RF (radio frequency) devices.


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