The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2013

Filed:

Jun. 30, 2009
Applicants:

Erich F. Haratsch, Bethlehem, PA (US);

Milos Ivkovic, Sunnyvale, CA (US);

Victor Krachkovsky, Allentown, PA (US);

Nenad Miladinovic, Campbell, CA (US);

Andrei Vityaev, San Jose, CA (US);

Johnson Yen, Fremont, CA (US);

Inventors:

Erich F. Haratsch, Bethlehem, PA (US);

Milos Ivkovic, Sunnyvale, CA (US);

Victor Krachkovsky, Allentown, PA (US);

Nenad Miladinovic, Campbell, CA (US);

Andrei Vityaev, San Jose, CA (US);

Johnson Yen, Fremont, CA (US);

Assignee:

LSI Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.


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