The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2013
Filed:
Mar. 02, 2012
Yiran Chen, Eden Prairie, MN (US);
Hai LI, Eden Prairie, MN (US);
Wenzhong Zhu, Apple Valley, MN (US);
Xiaobin Wang, Chanhasssen, MN (US);
Henry Huang, Apple Valley, MN (US);
Hongyue Liu, Maple Grove, MN (US);
Yiran Chen, Eden Prairie, MN (US);
Hai Li, Eden Prairie, MN (US);
Wenzhong Zhu, Apple Valley, MN (US);
Xiaobin Wang, Chanhasssen, MN (US);
Henry Huang, Apple Valley, MN (US);
Hongyue Liu, Maple Grove, MN (US);
Seagate Technology LLC, Cupertino, CA (US);
Abstract
The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.