The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2013
Filed:
Apr. 12, 2010
Arvind Chandrasekaran, San Diego, CA (US);
Brian Henderson, San Diego, CA (US);
Arvind Chandrasekaran, San Diego, CA (US);
Brian Henderson, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.