The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2013
Filed:
Jun. 26, 2012
Yung-fa Lin, Hsinchu, TW;
Shou-yi Hsu, Hsinchu County, TW;
Meng-wei Wu, Hsinchu, TW;
Main-gwo Chen, Hsinchu County, TW;
Chia-hao Chang, Hsinchu, TW;
Chia-wei Chen, Taipei, TW;
Yung-Fa Lin, Hsinchu, TW;
Shou-Yi Hsu, Hsinchu County, TW;
Meng-Wei Wu, Hsinchu, TW;
Main-Gwo Chen, Hsinchu County, TW;
Chia-Hao Chang, Hsinchu, TW;
Chia-Wei Chen, Taipei, TW;
Anpec Electronics Corporation, Hsinchu Science Park, Hsin-Chu, TW;
Abstract
The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.