The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2013
Filed:
Jun. 23, 2010
Ekaterina M. Ambroladze, Wappingers Falls, NY (US);
Deanna Postles Dunn Berger, Poughkeepsie, NY (US);
Michael Fee, Cold Spring, NY (US);
Arthur J. O'neill, Jr., Poughkeepsie, NY (US);
Diana Lynn Orf, Somerville, MA (US);
Robert J. Sonnelitter, Iii, Wappingers Falls, NY (US);
Ekaterina M. Ambroladze, Wappingers Falls, NY (US);
Deanna Postles Dunn Berger, Poughkeepsie, NY (US);
Michael Fee, Cold Spring, NY (US);
Arthur J. O'Neill, Jr., Poughkeepsie, NY (US);
Diana Lynn Orf, Somerville, MA (US);
Robert J. Sonnelitter, III, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.