The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2013

Filed:

Jun. 13, 2011
Applicants:

Kumar Nagarajan, San Jose, CA (US);

Raghunandan Chaware, Mountain View, CA (US);

Inventors:

Kumar Nagarajan, San Jose, CA (US);

Raghunandan Chaware, Mountain View, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, an interposer resistant to warping is provided. The interposer includes a semiconductor body having a first contact array included on a first side of the semiconductor body. Vias are formed through the semiconductor body. One or more wiring layers are included on the first side of the semiconductor body. The wiring layers electrically couple each contact of the first contact array to a respective one of the vias. Contacts of a second contact array, included on a second side of the semiconductor body, are respectively coupled to the vias. A stabilization layer is included on the second side of the semiconductor body. The stabilization layer is configured to counteract stresses exerted on a front side of the interposer due to thermal expansion of wiring layers.


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