The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2013

Filed:

Dec. 17, 2008
Applicants:

Lucie A. Rousseville, Waldolwisheim, FR;

Sebastien Jacqueline, Bernieres sur Mer, FR;

Patrice Gamand, Douvres la Delivrande, FR;

Dominique Yon, Saint Aubin sur Mer, FR;

Inventors:

Lucie A. Rousseville, Waldolwisheim, FR;

Sebastien Jacqueline, Bernieres sur Mer, FR;

Patrice Gamand, Douvres la Delivrande, FR;

Dominique Yon, Saint Aubin sur Mer, FR;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 29/10 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a method and system for testing integrity of a passivation layer () covering a semiconductor device. A structured layer of electrically conducting material () is deposited onto at least a portion of a top surface of a substrate () of the semiconductor device. The structured layer () comprises a plurality of bands () connected to at least two contacts () and disposed on the at least a portion of the top surface such that one of consecutive bands () and consecutive portions of the bands () are connected to different contacts (). A passivation layer () is deposited onto the at least a portion of the top surface of the substrate () and the structured layer () such that material of the passivation layer() is disposed between the bands of conducting material () and on top of the structured layer (). Electrically conducting material is then deposited onto the passivation layer () and a resistance is measured between the at least two contacts (). An indication with respect to integrity of the passivation layer () is determined in dependence upon the measured resistance.


Find Patent Forward Citations

Loading…