The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2013
Filed:
Apr. 13, 2012
Jin-mu Yin, Kaohsiung, TW;
Shyh-wei Wang, Hsinchu, TW;
Yen-ming Chen, Chu-Pei, TW;
Abstract
A method for manufacturing the integrated circuit device comprises providing a substrate having a first region, a second region, and a third region. A first dielectric layer is formed in the first region of the substrate. A second dielectric layer is formed in the second region and the third region. A sacrificial layer is formed over the first dielectric layer and the second dielectric layer. The sacrificial layer, the first dielectric layer, and the second dielectric layer are patterned to form a first gate stack, a second gate stack, and a third gate stack. An interlayer dielectric (ILD) layer is formed in between the first gate stack, the second gate stack, and the third gate stack. The second gate stack is removed to form an opening adjacent to the ILD layer and a third dielectric layer is formed in the opening.