The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
Sep. 22, 2010
Michael S. Bair, Banks, OR (US);
David W. Burns, Portland, OR (US);
Robert S. Chappell, Portland, OR (US);
Prakash Math, Portland, OR (US);
Leslie A. Ong, Portland, OR (US);
Pankaj Raghuvanshi, Hillsboro, OR (US);
Shlomo Raikin, Geva Carmel, IL;
Raanan Sade, Kibutz Gvat, IL;
Michael D. Tucknott, Hillsboro, OR (US);
Igor Yanover, Nesher, IL;
Michael S. Bair, Banks, OR (US);
David W. Burns, Portland, OR (US);
Robert S. Chappell, Portland, OR (US);
Prakash Math, Portland, OR (US);
Leslie A. Ong, Portland, OR (US);
Pankaj Raghuvanshi, Hillsboro, OR (US);
Shlomo Raikin, Geva Carmel, IL;
Raanan Sade, Kibutz Gvat, IL;
Michael D. Tucknott, Hillsboro, OR (US);
Igor Yanover, Nesher, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.