The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2013

Filed:

Jan. 31, 2011
Applicants:

Sanjay Gupta, Nioda, IN;

Charles W. Selvidge, Wellesley, MA (US);

Praveen Shukla, Allahabad, IN;

Inventors:

Sanjay Gupta, Nioda, IN;

Charles W. Selvidge, Wellesley, MA (US);

Praveen Shukla, Allahabad, IN;

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques and tool for selecting compilation parameter values for compiling a first description of a circuit design, such as a register transfer language description, into a second description of the circuit design, such as a model description for implementation with an emulator are provided. According to various examples of the invention, a compilation tool 'elaborates' the first description of the circuit design into a third description for the circuit design. Typically, the third description or 'elaboration' will cross one or more hierarchical boundaries represented in the first description of the circuit design, so that the elaboration will represent at least a portion of two or more hierarchical modules in the first description design according to a non-hierarchical or “flat” manner. Also, with some implementations of the invention, the elaboration may include only a simple representation of a corresponding portion of the circuit design.


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