The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2013

Filed:

Sep. 15, 2010
Applicants:

Donald S. Gardner, Mountain View, CA (US);

Gerhard Schrom, Hillsboro, OR (US);

Peter Hazucha, Beaverton, OR (US);

Fabrice Paillet, Hillsboro, OR (US);

Tanay Karnik, Portland, OR (US);

Inventors:

Donald S. Gardner, Mountain View, CA (US);

Gerhard Schrom, Hillsboro, OR (US);

Peter Hazucha, Beaverton, OR (US);

Fabrice Paillet, Hillsboro, OR (US);

Tanay Karnik, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/76 (2006.01); H01L 21/425 (2006.01); H01L 21/469 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.


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