The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
Nov. 17, 2011
Parviz Ghazavi, San Jose, CA (US);
Hieu Van Tran, San Jose, CA (US);
Shiuh-luen Wang, San Jose, CA (US);
Nhan DO, Saratoga, CA (US);
Henry A. Om'mani, Santa Clara, CA (US);
Parviz Ghazavi, San Jose, CA (US);
Hieu Van Tran, San Jose, CA (US);
Shiuh-Luen Wang, San Jose, CA (US);
Nhan Do, Saratoga, CA (US);
Henry A. Om'mani, Santa Clara, CA (US);
Silicon Storage Technology, Inc., San Jose, CA (US);
Abstract
An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.