The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2013
Filed:
Jan. 25, 2011
Takashi Ando, Tackahoe, NY (US);
Leslie Charns, San Jose, CA (US);
Jason E. Cummings, Smithfield, NC (US);
Lukasz J. Hupka, Croton-On-Hudson, NY (US);
Dinesh R. Koli, Tarrytown, NY (US);
Tomohisa Konno, Mie, JP;
Mahadevaiyer Krishnan, Hopewell Junction, NY (US);
Michael F. Lofaro, Danbury, CT (US);
Jakub W. Nalaskowski, Yorktown Heights, NY (US);
Masahiro Noda, Mie, JP;
Dinesh K. Penigalapati, Tarrytown, NY (US);
Tatsuya Yamanaka, Mie, JP;
Takashi Ando, Tackahoe, NY (US);
Leslie Charns, San Jose, CA (US);
Jason E. Cummings, Smithfield, NC (US);
Lukasz J. Hupka, Croton-On-Hudson, NY (US);
Dinesh R. Koli, Tarrytown, NY (US);
Tomohisa Konno, Mie, JP;
Mahadevaiyer Krishnan, Hopewell Junction, NY (US);
Michael F. Lofaro, Danbury, CT (US);
Jakub W. Nalaskowski, Yorktown Heights, NY (US);
Masahiro Noda, Mie, JP;
Dinesh K. Penigalapati, Tarrytown, NY (US);
Tatsuya Yamanaka, Mie, JP;
International Business Machines Corporation, Armonk, NY (US);
JRS Corporation, Tokyo, JP;
Abstract
Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.