The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2013
Filed:
Feb. 01, 2010
Yung-chin Hou, Taipei, TW;
David Barry Scott, Plano, TX (US);
Lee-chung LU, Taipei, TW;
Li-chun Tien, Tainan, TW;
Yung-Chin Hou, Taipei, TW;
David Barry Scott, Plano, TX (US);
Lee-Chung Lu, Taipei, TW;
Li-Chun Tien, Tainan, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.