The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2013
Filed:
Sep. 13, 2012
Kar Keng Chua, Penang, MY;
Sammy Cheung, South San Francisco, CA (US);
Hee Kong Phoon, Perak, MY;
Kim Pin Tan, Penang, MY;
Wei Lian Goay, Penang, MY;
Kar Keng Chua, Penang, MY;
Sammy Cheung, South San Francisco, CA (US);
Hee Kong Phoon, Perak, MY;
Kim Pin Tan, Penang, MY;
Wei Lian Goay, Penang, MY;
Altera Corporation, San Jose, CA (US);
Abstract
Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements ('HLEs'), each of which can provide a portion of the full functionality of an FPGA logic element ('LE'). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.