Calculation of integrated circuit timing delay using frequency domain

Abstract

Accurate circuit and system timing analysis is a critical tool for designing and analyzing complex modern semiconductor chips. While the accuracy and detail of dynamic electrical simulation may be desirable in theory, such analysis is not feasible due to extreme computational complexity and open-ended simulation times. Improved circuit modeling and timing analysis tools that can provide both accuracy and computational efficiency are required. Table look-up (TLU) and other techniques provide computationally efficient timing analysis but may be undertaken at the expense of simulation accuracy. Instead, the use of current waveform moments representing the frequency domain equivalents of signals can provide the required simulation accuracy and computational efficiency.