The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2013
Filed:
Jun. 22, 2011
Stéphane Le Tual, Saint Egreve, FR;
Pratap Narayan Singh, Varanasi, IN;
Oleksiy Zabroda, Orleans, CA;
Nicola Vannucci, Pisa, IT;
Stéphane Le Tual, Saint Egreve, FR;
Pratap Narayan Singh, Varanasi, IN;
Oleksiy Zabroda, Orleans, CA;
Nicola Vannucci, Pisa, IT;
STMicroelectronics S.A., Montrouge, FR;
STMicroelectronics Pvt. Ltd., Greater Noida, IN;
STMicroelectronics (Canada) Inc., Nepean, CA;
STMicroelectronics S.r.l., Agrate Brianza (MI), IT;
Abstract
A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.