Multiple electrode layer backend stacked capacitor

Abstract

In a disclosed embodiment, a stacked capacitor () has bottom, middle and top metal electrode layers (A,B,C) interleaved with dielectric layers (A,B) conformally disposed within holes (A,B,C) in a protective overcoat or backend dielectric layer () over a top metal layer () of an integrated circuit (). A top electrode () contacts the top metal electrode layer (C). A bottom electrode () electrically couples an isolated part of the top metal electrode layer (C) through a bottom electrode via (A) to a first contact node (A) in the top metal layer () which is in contact with the bottom metal electrode layer (A). A middle electrode () electrically couples a part of the middle metal electrode layer (B) not covered by the top metal layer () through a middle electrode via (B) to a second contact node (B) in the top metal electrode layer (). The sidewalls of the top and middle electrode vias (A,B) are lined with insulating material to electrically isolate the metal electrode layer ends.