The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2013

Filed:

Sep. 22, 2011
Applicants:

Young-seung Cho, Yongin-si, KR;

Dae-ik Kim, Yongin-si, KR;

Yoo-sang Hwang, Suwon-si, KR;

Hyun-woo Chung, Seoul, KR;

Inventors:

Young-seung Cho, Yongin-si, KR;

Dae-ik Kim, Yongin-si, KR;

Yoo-sang Hwang, Suwon-si, KR;

Hyun-woo Chung, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/76 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a semiconductor device including a vertical channel transistor. The method may include: forming a plurality of first device isolation layers in a substrate as a pattern of lines having a first depth from an upper surface of a substrate, to define a plurality of active regions, forming a plurality of trenches having a second depth smaller than the first depth, etching portions of the substrate that are under some of the plurality of trenches that are selected at a predetermined interval, to form a plurality of device isolation trenches having a third depth that is greater than the second depth, forming second device isolation layers that include an insulating material, in lower portions of the plurality of device isolation trenches, and forming buried bit lines in lower portions of the plurality of trenches and the plurality of device isolation trenches.


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